This application claims the priority benefit of Taiwan application serial no. 89126421, filed Dec. 12, 2000.
1. Field of Invention
The present invention relates to an integrated circuit device and method of manufacture. More particularly, the present invention relates to a cylindrical capacitor structure and a corresponding method of manufacture that is especially suitable for fabricating dynamic random access memory (DRAM).
2. Description of Related Art
In general, a dynamic random access memory (DRAM) mainly consists of a metal-oxide-semiconductor (MOS) transistor and a capacitor. To increase the capacitance of the capacitor and reduce possible data errors and refreshing frequency, the capacitor is stacked on top of a bit line, thereby increasing the cross-sectional area. This is the so-called capacitor on bit (COB) line structure. In addition, for further increasing the surface area of a capacitor, a three-dimensional lower electrode is often formed inside the COB structure. The three-dimensional lower electrode can be a cylindrical lower electrode formed, for example, inside an opening in the dielectric layer above a node contact. The node contact electrically connects the lower electrode and the source/drain region of a MOS transistor.
A conventional DRAM cylindrical capacitor manufacturing includes the following steps. First, a substrate having a metal-oxide-semiconductor transistor thereon is provided. A first insulation layer is formed over the MOS transistor. A landed via is formed in the first insulation layer. The landed via is in electrical contact with a source/drain region of the MOS transistor. A second insulation layer is formed over the substrate and then a bit line is formed over the second insulation layer. A third insulation layer is formed over the bit line and then a first photolithographic and a first etching process are conducted. In the etching step, the second and the third insulation layer between the bit lines are etched through to form a node contact opening that exposes the landed via above the drain terminal. Polysilicon is next deposited into the node contact opening to form a node contact. A fourth insulation layer is formed over the substrate and then a cylindrical opening is formed in the fourth insulation layer so that a portion of the node contact is exposed. A first conformal conductive layer is formed over the substrate and then chemical-mechanical polishing (CMP) is conducted to remove the first conductive layer outside the cylindrical opening. A portion of the first conductive is retained to become a cylindrical lower electrode of a capacitor. The lower electrode is in electrical contact with node contact. A dielectric layer is formed over the lower electrode and then a second conductive layer is formed over the dielectric layer. A second photolithographic process and a second etching process is conducted to pattern the second conductive layer, thereby forming the upper electrode.
In the aforementioned method of manufacturing the cylindrical capacitor, photolithographic and etching process is performed twice. Moreover, the process of removing the first conductive layer outside the cylindrical opening by polishing often results in some residual slurry clinging to the surface of the cylindrical opening. The residual slurry may contaminate the material during backend processes.
Accordingly, one object of the present invention is to provide a method of manufacturing a cylindrical capacitor, especially suitable for fabricating dynamic random access memory (DRAM). A conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. The bit line structure includes a cap layer above the bit line and spacers on the sidewalls of the bit line. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Width of each gap is smaller than the node contact opening. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. Up to this point, the originally linked cylindrical openings are no longer connected. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited into the node contact openings and the cylindrical openings to become the lower electrodes and the node contacts respectively.
This invention also provides a cylindrical capacitor structure that can be applied to the fabrication of DRAM devices. The cylindrical capacitor structure is formed by the aforementioned method. The cylindrical capacitor structure has an upper electrode that includes a layer of conductive material filling gaps and linking various conductive spacers of an identical material. The conductive spacers are located on the sidewalls of various cylindrical openings and node contact openings. The gaps are located between various cylindrical opening. In addition, the lower electrode of the capacitor is formed by filling the inner surface of the dielectric layer constituting the cylindrical openings. In fact, the upper and lower electrode of the capacitor in this invention is positioned in reverse to that of a conventional cylindrical capacitor.
The conductive section can be a landed via above the source/drain region of a MOS transistor or the source/drain region of a MOS transistor, for example.
This invention integrates the process of patterning out a mold (space that links the cylindrical openings and the gaps) for forming the upper electrode and the process of patterning the node contact openings and the cylindrical openings. Furthermore, width of the gap between the cylindrical openings is sufficiently narrow so that the cylindrical opening for accommodating the lower electrode can be separated out after complete formation of the upper electrode. Consequently, processing step in this invention is simplified because there is no need to perform photolithographic and etching process twice just to pattern out the upper electrode and the node contact opening. In addition, the lower electrode of the capacitor is formed by filling the inner surface of the dielectric layer that constitutes the cylindrical opening. Since there is no need to perform chemical-mechanical polishing, contamination by slurry can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.